Due to the intense demand for a high-density memory in the semiconductor industry (for example, floating gate memory, charge trapping memory, non-volatile memory, and embedded memory), the architecture of a memory cell has transitioned from a planar structure to a 3-dimensional structure, which increases the storage capacity within a limited chip area. A cross-point array is one form of 3D memory structures that includes a plurality of word-lines, a plurality of bit-lines, and a memory layer sandwiched between the word-lines and the bit-lines.
Along the process of scaling, not only has the dimension of the bit-line (and word-line) themselves shrunk but also the distance therebetween. In terms of the cross-point arrays, the aspect ratio of the bit-line constantly increases in pursuing an even higher storage capacity by creating multiple memory cells in a single footprint of the cross-point. The problem regarding the high aspect ratio also applied to the processing of word-line due to the stacking structure of the 3D memory. A pattern-defining procedure such as an anisotropic etch faces a more stringent condition because of the high aspect ratio and the narrow space between the bit-lines (and word-lines). Bridging effect occurs as a result of creating the above-mentioned pattern and causes operational failure of the memory device.
In a conventional cross-point 3D memory structure, word-line to word-line coupling becomes a serious problem when the spaces between the word-lines decline. Word-line coupling can be attributed to longer word-lines and narrower spacing, and of course, the conventional 3D memory structure forms a high overlapping area between adjacent word-lines, and hence, increases the coupling capacitance.
3D memory structures that effectively overcome the bridging and coupling effect are, therefore, desired. However, said structure would be of greater demand if the manufacturing process is straightforward and the processing cost is controlled.